POWER CONTROL AND OPTIMIZATION: Proceedings of the 7th Global Conference on Power Control and Optimization

 

Conference date: 2728 August and 2-3 December 2013

Location: Prague (Czech Republic) and Yangon (Myanmar)

ISBN:  978-983-44483-63

Editors: Ivan Zelinka, Zeya Oo and Nader Barsoum

Volume number: 2008

Published: 15 April 2013

 

 

 

Multiple Valued Logic (MVL) Reduction Operator, its Synthesis and Application on Network Congestion

Adib Kabir Chowdhury, Muhammad Ibrahim, Veeramani Shanmugam, Ashutosh Kumar Singh

PCO Conf-Proc 2008 (2013), - PDF

 

 

Abstract. In this paper, reduction logical operator (RLO) has been proposed to control bottleneck link size by realizing Multi-Valued Logic (MVL) function. A novel Switch Delay Link Mechanism (SDLM) Algorithm using Transmission Control Protocol (TCP) has been represented to serve as a basic input generator for base and reduced link size of the network bottleneck, which gives input to the RLO. On the other hand, the SDLM algorithm produces base and reduced latency, which is later fed to the RLO for better performance. A complete RLO function can be further synthesized to obtain faster and efficient data processing. SDLM algorithm merges with RLO operator to overcome the network congestion problem of fixed networks. The advantages of RLO-SDLM algorithm is demonstrated with packet drop in fixed networks. The comparison against RLO-SDLM algorithm is based on the usage of network bottleneck link size and the delay to determine the sending rate and packet loss. Overall the algorithm shows an average improvement of 0.52% compared to the other existing algorithm. We used NS2 software simulator to experiment different set of flows to achieve an optimum result.

 

2013 PCO based on American Institute of Physics